-- $id: $MG84
-- File name:   MEM_CTLR.vhd
-- Created:     11/4/2010
-- Author:      Cody Farmer
-- Lab Section: 337-004
-- Version:     2.0 Design Entry
-- Description: Memory Control for Group Final Project. Will store and retrieve data from an off-chip SRAM devide.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
entity MEM_CTL is
port(
	clk: in std_logic;
	RST_N : in std_logic;
	log: in std_logic;
	empty : in std_logic;
	full : in std_logic;
	RCVING : in std_logic;
	WE : out std_logic;  --nWriteEnable
	RE : out std_logic;  --nOutputEnable
	--memWAIT : in std_logic;  --SRAM busy signal
	R_ENABLE : out std_logic;
	W_ENABLE : out std_logic;
	ADDR : out std_logic_vector(15 downto 0)  -- Address of SRAM to store to
);
end MEM_CTL;

architecture behavioral of MEM_CTL is 
  type stateType is (IDLE,STOREUP,STORE,LOAD, EIDLE);
  signal state,nextstate : stateType;
  signal count,nextcount,count2,nextcount2 : std_logic_vector(15 downto 0);
begin
  process(clk,RST_N)
  begin
    if RST_N = '0' then
      state <= idle;
      count <= (others => '0');
      count2 <= "0000000000000000";
    elsif rising_edge(clk) then
      state <= nextstate;
      count <= nextcount;
      count2 <= nextcount2;
    end if;
  end process;

  NXTSTATE:process(state,nextstate,empty,log,RCVING)
  begin
    nextcount <= count;
    nextcount2 <= count2;
  
    case state is
      when IDLE =>
        if LOG = '0' then
          nextstate <= STORE;
        else 
          nextstate <= LOAD;
        end if;

      when STORE =>
        if (empty = '0')  then
          nextstate <= STOREUP;			
        else
	  nextstate <= STORE;
        end if;

        if empty = '1' then
		      nextstate <= EIDLE;
        end if;

      when STOREUP =>
	 nextstate <= IDLE;	
    	 nextcount <= count + 2;

      when LOAD =>
        if nextcount2 = nextcount then
          nextstate <= EIDLE;
        end if;
    	if full = '0' then
        nextcount2 <= count2 + 2;
        nextstate <= IDLE;
	else
	nextstate <= EIDLE;
	end if;    

      when EIDLE =>
        nextstate <= IDLE;

    end case;
  end process;

  Logic:process(state)
  begin
    WE <= '0';  --nWriteEnable
    RE <= '0';  --nReadEnable
    R_ENABLE <= '0';
    W_ENABLE <= '0';

    case state is
      when IDLE =>


      when STORE =>


      when STOREUP =>
         R_ENABLE <= '1';
	 WE <= '1';
	 ADDR <= count;

      when LOAD =>
	  W_ENABLE <= '1';
	  RE <= '1';
	  ADDR <= count2;

      when eidle =>

    end case;
  end process;
end behavioral;
